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| www.fairchildsemi.com rev. 1.0.5 9/25/01 features ? internally synchronized leading-edge pfc and trailing- edge pwm in one ic ? trifault detect? for ul1950 compliance and enhanced safety ? slew rate enhanced transconductance error ampli?er for ultra-fast pfc response ? low power: 200a startup current, 5.5ma operating current ? low total harmonic distortion, high pf ? reduced ripple current in storage capacitor between pfc and pwm sections ? average current, continuous boost leading edge pfc ? pwm con?gurable for current-mode or voltage mode operation ? current fed gain modulator for improved noise immunity ? overvoltage and brown-out protection, uvlo, and soft start general description the ml4800 is a controller for power factor corrected, switched mode power supplies. power factor correction (pfc) allows the use of smaller, lower cost bulk capacitors, reduces power line loading and stress on the switching fets, and results in a power supply that fully complies with iec1000-3-2 speci?cation. intended as a bicmos version of the industry-standard ml4824, the ml4800 includes circuits for the implementation of leading edge, average current, boost type power factor correction and a trailing edge, pulse width modulator (pwm). it also includes a trifault detect? function to help ensure that no unsafe conditions will result from single component failure in the pfc. gate-drivers with 1a capabilities minimize the need for external driver circuits. low power requirements improve ef?ciency and reduce component costs. an over-voltage comparator shuts down the pfc section in the event of a sudden decrease in load. the pfc section also includes peak current limiting and input voltage brownout protection. the pwm section can be operated in current or voltage mode, at up to 250khz, and includes an accurate 50% duty cycle limit to prevent transformer saturation. block diagram 15 veao ieao v fb i ac v rms i sense ramp 1 oscillator ovp pfc i limit uvlo v ref pulse width modulator power factor corrector tri-fault 2.5v + - - + 16 2 4 3 7.5v reference 14 v cc 13 v cc vea 7 - + iea 1 + - + - + - pfc out 12 s r q q s r q q 2.75v 0.5v -1v ramp 2 8 pwm out 11 s r q q v dc 6 ss 5 dc i limit 9 v cc duty cycle limit - + 1.0v - + 2.45v v fb - + v ref v in ok gain modulator v cc 1.6k ? 1.6k ? 1.25v 25 a - + dc i limit 17v ml4800 power factor correction and pwm controller combo
ml4800 product specification 2 rev. 1.0.5 9/25/01 pin con?uration pin description pin name function 1 ieao slew rate enhanced pfc transconductance error amplifier output 2i ac pfc ac line reference input to gain modulator 3i sense current sense input to the pfc gain modulator 4v rms pfc gain modulator rms line voltage compensation input 5 ss connection point for the pwm soft start capacitor 6v dc pwm voltage feedback input 7 ramp 1 oscillator timing node; timing set by r t c t 8 ramp 2 when in current mode, this pin functions as the current sense input; when in voltage mode, it is the pwm modulation ramp input. 9 dc i limit pwm cycle-by-cycle current limit comparator input 10 gnd ground 11 pwm out pwm driver output 12 pfc out pfc driver output 13 v cc positive supply 14 v ref buffered output for the internal 7.5v reference 15 v fb pfc transconductance voltage error amplifier input 16 veao pfc transconductance voltage error amplifier output 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 ieao i ac i sense v rms ss v dc ramp 1 ramp 2 veao v fb v ref v cc pfc out pwm out gnd dc i limit top view ml4800 16-pin pdip (p16) 16-pin narrow soic (s16n) product specification ml4800 rev. 1.0.5 9/25/01 3 abolute maximum ratings absolute maximum ratings are those values beyond which the device could be permanently damaged. absolute maximum rat- ings are stress ratings only and functional device operation is not implied. operating conditions parameter min. max. units v cc 18 v i sense voltage -5 0.7 v voltage on any other pin gnd - 0.3 v ccz + 0.3 v i ref 10 ma i ac input current 10 ma peak pfc out current, source or sink 1 a peak pwm out current, source or sink 1 a pfc out, pwm out energy per cycle 1.5 ? junction temperature 150 ? storage temperature range -65 150 ? lead temperature (soldering, 10 sec) 260 ? thermal resistance ( ja ) plastic dip plastic soic 80 105 ?/w ?/w temperature range min .max. units ml4800cx 0 70 c ml4800ix -40 85 ? electrical characteristics unless otherwise speci?d, v cc = 15v, r t = 52.3k ? , c t = 470pf, t a = operating temperature range (note 1) symbol parameter conditions min. typ. max. units voltage error ampli?r input voltage range 0 5 v transconductance v non inv = v inv , veao = 3.75v 30 65 90 ? feedback reference voltage 2.43 2.5 2.57 v input bias current note 2 -0.5 -1.0 ? output high voltage 6.0 6.7 v output low voltage 0.1 0.4 v source current v in = ?.5v, v out = 6v -40 -140 ? sink current v in = ?.5v, v out = 1.5v 40 140 ? open loop gain 50 60 db power supply rejection ratio 11v < v cc < 16.5v 50 60 db current error ampli?r input voltage range -1.5 2 v transconductance v non inv = v inv , veao = 3.75v 50 100 150 ? input offset voltage 0 4 15 mv ? ? ml4800 product specification 4 rev. 1.0.5 9/25/01 input bias current -0.5 -1.0 ? output high voltage 6.0 6.7 v output low voltage 0.65 1.0 v source current v in = ?.5v, v out = 6v -40 -104 ? sink current v in = ?.5v, v out = 1.5v 40 160 ? open loop gain 60 70 db power supply rejection ratio 11v < v cc < 16.5v 60 75 db ovp comparator threshold voltage 2.65 2.75 2.85 v hysteresis 175 250 325 mv tri-fault detect fault detect high 2.65 2.75 2.85 v time to fault detect high v fb = v fault detect low to v fb = open. 470pf from v fb to gnd 24ms fault detect low 0.4 0.5 0.6 v pfc i limit comparator threshold voltage -0.9 -1.0 -1.1 v (pfc i limit v th - gain modulator output) 120 220 mv delay to output 150 300 ns dc i limit comparator threshold voltage 0.95 1.0 1.05 v input bias current ?.3 ? ? delay to output 150 300 ns v in ok comparator threshold voltage 2.35 2.45 2.55 v hysteresis 0.8 1.0 1.2 v gain modulator gain (note 3) i ac = 100?, v rms = v fb = 0v 0.60 0.80 1.05 i ac = 50?, v rms = 1.2v, v fb = 0v 1.8 2.0 2.40 i ac = 50?, v rms = 1.8v, v fb = 0v 0.85 1.0 1.25 i ac = 100?, v rms = 3.3v, v fb = 0v 0.20 0.30 0.40 bandwidth i ac = 100? 10 mhz output voltage i ac = 350?, v rms = 1v, v fb = 0v 0.60 0.75 0.9 v oscillator initial accuracy t a = 25? 71 76 81 khz voltage stability 11v < v cc < 16.5v 1 % temperature stability 2 % total variation line, temp 68 84 khz ramp valley to peak voltage 2.5 v electrical characteristics (continued) unless otherwise speci?d, v cc = 15v, r t = 52.3k ? , c t = 470pf, t a = operating temperature range (note 1) symbol parameter conditions min. typ. max. units product specification ml4800 rev. 1.0.5 9/25/01 5 notes 1. limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions. 2. includes all bias currents to other circuits connected to the v fb pin. 3. gain = k x 5.3v; k = (i gainmod - i offset ) x [i ac (veao - 0.625)] -1 ; veao max =5v. pfc dead time 350 650 ns c t discharge current v ramp 2 = 0v, v ramp 1 = 2.5v 3.5 5.5 7.5 ma reference output voltage t a = 25?, i(v ref ) = 1ma 7.4 7.5 7.6 v line regulation 11v ml4800 product specification 6 rev. 1.0.5 9/25/01 typical performance characteristics variable gain block constant (k) vrms(v) 0245 13 480 420 360 300 240 180 120 60 0 180 160 140 120 100 80 60 40 20 0 transconductance ( ) v fb (v) 05 3 14 2 ? 180 160 140 120 100 80 60 40 20 0 transconductance ( ) iea input voltage (mv) 500 500 0 ? voltage error amplifier (vea) transconductance (g m ) current error amplifier (iea) transconductance (g m ) gain modulator transfer characteristic (k) k i gainmod 84 a C () iac 5 0.625 C () ---------------------------------------------------- -mv 1 C = product specification ml4800 rev. 1.0.5 9/25/01 7 functional description the ml4800 consists of an average current controlled, continuous boost power factor corrector (pfc) front end and a synchronized pulse width modulator (pwm) back end. the pwm can be used in either current or voltage mode. in voltage mode, feedforward from the pfc output buss can be used to improve the pwms line regulation. in either mode, the pwm stage uses conventional trailing- edge duty cycle modulation, while the pfc uses leading- edge modulation. this patented leading/trailing edge modu- lation technique results in a higher usable pfc error ampli- ?er bandwidth, and can signi?cantly reduce the size of the pfc dc buss capacitor. the synchronization of the pwm with the pfc simpli?es the pwm compensation due to the controlled ripple on the pfc output capacitor (the pwm input capacitor). the pwm sec- tion of the ml4800 runs at the same frequency as the pfc. in addition to power factor correction, a number of protec- tion features have been built into the ml4800. these include soft-start, pfc overvoltage protection, peak current limiting, brownout protection, duty cycle limiting, and under-voltage lockout. power factor correction power factor correction makes a nonlinear load look like a resistive load to the ac line. for a resistor, the current drawn from the line is in phase with and proportional to the line voltage, so the power factor is unity (one). a common class of nonlinear load is the input of most power supplies, which use a bridge recti?er and capacitive input ?lter fed from the line. the peak-charging effect, which occurs on the input ?l- ter capacitor in these supplies, causes brief high-amplitude pulses of current to ?ow from the power line, rather than a sinusoidal current inphase with the line voltage. such sup- plies present a power factor to the line of less than one (i.e. they cause signi?cant current harmonics of the power line frequency to appear at their input). if the input current drawn by such a supply (or any other nonlinear load) can be made to follow the input voltage in instantaneous amplitude, it will appear resistive to the ac line and a unity power factor will be achieved. to hold the input current draw of a device drawing power from the ac line in phase with and proportional to the input voltage, a way must be found to prevent that device from loading the line except in proportion to the instantaneous line voltage. the pfc section of the ml4800 uses a boost-mode dc-dc converter to accomplish this. the input to the con- verter is the full wave recti?ed ac line voltage. no bulk ?l- tering is applied following the bridge recti?er, so the input voltage to the boost converter ranges (at twice line fre- quency) from zero volts to the peak value of the ac input and back to zero. by forcing the boost converter to meet two simultaneous conditions, it is possible to ensure that the cur- rent drawn from the power line is proportional to the input line voltage. one of these conditions is that the output volt- age of the boost converter must be set higher than the peak value of the line voltage. a commonly used value is 385vdc, to allow for a high line of 270vac rms . the other condition is that the current drawn from the line at any given instant must be proportional to the line voltage. establishing a suitable voltage control loop for the converter, which in turn drives a current error ampli?er and switching output driver satis?es the ?rst of these requirements. the second requirement is met by using the recti?ed ac line voltage to modulate the output of the voltage control loop. such modulation causes the current error ampli?er to command a power stage current that varies directly with the input voltage. in order to prevent ripple, which will necessarily appear at the output of the boost circuit (typically about 10vac on a 385v dc level), from introducing distortion back through the voltage error ampli?er, the bandwidth of the voltage loop is deliberately kept low. a ?nal re?nement is to adjust the overall gain of the pfc such to be propor- tional to 1/v in 2, which linearizes the transfer function of the system as the ac input voltage varies. since the boost converter topology in the ml4800 pfc is of the current-averaging type, no slope compensation is required. pfc section gain modulator figure 1 shows a block diagram of the pfc section of the ml4800. the gain modulator is the heart of the pfc, as it is this circuit block which controls the response of the current loop to line voltage waveform and frequency, rms line volt- age, and pfc output voltage. there are three inputs to the gain modulator. these are: 1. a current representing the instantaneous input voltage (amplitude and waveshape) to the pfc. the rectified ac input sine wave is converted to a proportional current via a resistor and is then fed into the gain modulator at i ac . sampling current in this way minimizes ground noise, as is required in high power switching power conversion environments. the gain modulator responds linearly to this current. 2. a voltage proportional to the long-term rms ac line voltage, derived from the rectified line voltage after scaling and filtering. this signal is presented to the gain modulator at v rms . the gain modulator s output is inversely proportional to v rms 2 (except at unusually low values of v rms where special gain contouring takes over, to limit power dissipation of the circuit components under heavy brownout conditions). the relationship between v rms and gain is called k, and is illustrated in the typical performance characteristics. 3. the output of the voltage error amplifier, veao. the gain modulator responds linearly to variations in this voltage. ml4800 product specification 8 rev. 1.0.5 9/25/01 the output of the gain modulator is a current signal, in the form of a full wave recti?ed sinusoid at twice the line fre- quency. this current is applied to the virtual-ground (nega- tive) input of the current error ampli?er. in this way the gain modulator forms the reference for the current error loop, and ultimately controls the instantaneous current draw of the pfc from the power line. the general form for the output of the gain modulator is: more exactly, the output current of the gain modulator is given by: where k is in units of v -1 . note that the output current of the gain modulator is limited to 500a. current error amplier the current error ampli?ers output controls the pfc duty cycle to keep the average current through the boost inductor a linear function of the line voltage. at the inverting input to the current error ampli?er, the output current of the gain modulator is summed with a current which results from a negative voltage being impressed upon the i sense pin. the negative voltage on i sense represents the sum of all currents ?owing in the pfc circuit, and is typically derived from a current sense resistor in series with the negative terminal of the input bridge recti?er. in higher power applications, two current transformers are sometimes used, one to monitor the id of the boost mosfet(s) and one to monitor the i f of the boost diode. as stated above, the inverting input of the cur- rent error ampli?er is a virtual ground. given this fact, and the arrangement of the duty cycle modulator polarities inter- nal to the pfc, an increase in positive current from the gain modulator will cause the output stage to increase its duty cycle until the voltage on i sense is adequately negative to cancel this increased current. similarly, if the gain modula- tors output decreases, the output duty cycle will decrease, to achieve a less negative voltage on the i sense pin. cycle-by-cycle current limiter the i sense pin, as well as being a part of the current feed- back loop, is a direct input to the cycle-by-cycle current limiter for the pfc section. should the input voltage at this pin ever be more negative than -1v, the output of the pfc will be disabled until the protection ?ip-?op is reset by the clock pulse at the start of the next pfc power cycle. trifault detect tm to improve power supply reliability, reduce system compo- nent count, and simplify compliance to ul 1950 safety standards, the ml4800 includes trifault detect. this feature monitors vfb (pin 15) for certain pfc fault conditions. in the case of a feedback path failure, the output of the pfc could go out of safe operating limits. with such a failure, vfb will go outside of its normal operating area. should vfb go too low, too high, or open, trifault detect senses the error and terminates the pfc output drive. trifault detect is an entirely internal circuit. it requires no external components to serve its protective function. overvoltage protection the ovp comparator serves to protect the power circuit from being subjected to excessive voltages if the load should suddenly change. a resistor divider from the high voltage dc output of the pfc is fed to v fb . when the voltage on v fb exceeds 2.75v, the pfc output driver is shut down. the pwm section will continue to operate. the ovp comparator has 250mv of hysteresis, and the pfc will not restart until the voltage at v fb drops below 2.50v. the v fb should be set at a level where the active and passive external power components and the ml4800 are within their safe operating voltages, but not so low as to interfere with the boost voltage regulation loop. i gainmod i ac veao v rms 2 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 1v = (1) i gainmod k veao 0.625v C () i ac = figure 1. pfc section block diagram 15 veao ieao v fb i ac v rms i sense ramp 1 oscillator ovp pfc i limit tri-fault 2.5v + + 16 2 4 3 vea 7 + iea 1 + + pfc out 12 s r q q s r q q 2.75v 1v + 0.5v 1.6k ? 1.6k ? gain modulator product specification ml4800 rev. 1.0.5 9/25/01 9 error amplier compensation the pwm loading of the pfc can be modeled as a negative resistor; an increase in input voltage to the pwm causes a decrease in the input current. this response dictates the proper compensation of the two transconductance error ampli?ers. figure 2 shows the types of compensation networks most commonly used for the voltage and current error ampli?ers, along with their respective return points. the current loop compensation is returned to v ref to produce a soft-start characteristic on the pfc: as the reference voltage comes up from zero volts, it creates a differentiated voltage on ieao which prevents the pfc from immediately demanding a full duty cycle on its boost converter. there are two major concerns when compensating the voltage loop error ampli?er; stability and transient response. optimizing interaction between transient response and stability requires that the error ampli?ers open-loop cross- over frequency should be 1/2 that of the line frequency, or 23hz for a 47hz line (lowest anticipated international power frequency). the gain vs. input voltage of the ml4800s voltage error ampli?er has a specially shaped non-linearity such that under steady-state operating conditions the transconductance of the error ampli?er is at a local minimum. rapid perturbations in line or load conditions will cause the input to the voltage error ampli?er (v fb ) to deviate from its 2.5v (nominal) value. if this happens, the transconductance of the voltage error ampli?er will increase signi?cantly, as shown in the typical performance charac- teristics. this raises the gain-bandwidth product of the voltage loop, resulting in a much more rapid voltage loop response to such perturbations than would occur with a conventional linear gain characteristic. the current ampli?er compensation is similar to that of the voltage error ampli?er with the exception of the choice of crossover frequency. the crossover frequency of the current ampli?er should be at least 10 times that of the voltage ampli?er, to prevent interaction with the voltage loop. it should also be limited to less than 1/6th that of the switching frequency, e.g. 16.7khz for a 100khz switching frequency. there is a modest degree of gain contouring applied to the transfer characteristic of the current error ampli?er, to increase its speed of response to current-loop perturbations. however, the boost inductor will usually be the dominant factor in overall current loop response. therefore, this contouring is signi?cantly less marked than that of the voltage error ampli?er. this is illustrated in the typical performance characteristics. for more information on compensating the current and voltage control loops, see application notes 33 and 34. application note 16 also contains valuable information for the design of this class of pfc. figure 2. compensation network connections for the voltage and current error amplifiers figure 3. external component connections to v cc 15 veao ieao v fb i ac v rms i sense 2.5v + 16 2 4 3 vea + iea + v ref 1 pfc output gain modulator ml4800 v cc gnd v bias 0.22 f ceramic 15v zener r bias ml4800 product specification 10 rev. 1.0.5 9/25/01 oscillator (ramp 1) the oscillator frequency is determined by the values of r t and c t , which determine the ramp and off-time of the oscillator output clock: the dead time of the oscillator is derived from the following equation: at v ref = 7.5v: the dead time of the oscillator may be determined using: the dead time is so small (tramp >> t deadtime ) that the operating frequency can typically be approximated by: example: for the application circuit shown in the data sheet, with the oscillator running at: solving for r t x c t yields 1.96 x 10 -4 . selecting standard components values, c t = 390pf, and r t = 51.1k ? . the dead time of the oscillator adds to the maximum pwm duty cycle (it is an input to the duty cycle limiter). with zero oscillator dead time, the maximum pwm duty cycle is typically 45%. in many applications, care should be taken that c t not be made so large as to extend the maximum duty cycle beyond 50%. this can be accomplished by using a stable 390pf capacitor for c t . pwm section pulse width modulator the pwm section of the ml4800 is straightforward, but there are several points which should be noted. foremost among these is its inherent synchronization to the pfc section of the device, from which it also derives its basic timing. the pwm is capable of current-mode or voltage mode operation. in current-mode applications, the pwm ramp (ramp 2) is usually derived directly from a current sensing resistor or current transformer in the primary of the output stage, and is thereby representative of the current ?owing in the converters output stage. dc i limit , which provides cycle-by-cycle current limiting, is typically con- nected to ramp 2 in such applications. for voltage-mode operation or certain specialized applications, ramp 2 can be connected to a separate rc timing network to generate a voltage ramp against which v dc will be compared. under these conditions, the use of voltage feedforward from the pfc buss can assist in line regulation accuracy and response. as in current mode operation, the dc i limit input is used for output stage overcurrent protection. no voltage error ampli?er is included in the pwm stage of the ml4800, as this function is generally performed on the output side of the pwms isolation boundary. to facilitate the design of optocoupler feedback circuitry, an offset has been built into the pwms ramp 2 input which allows v dc to command a zero percent duty cycle for input voltages below 1.25v. pwm current limit the dc i limit pin is a direct input to the cycle-by-cycle current limiter for the pwm section. should the input voltage at this pin ever exceed 1v, the output of the pwm will be disabled until the output ?ip-?op is reset by the clock pulse at the start of the next pwm power cycle. v in ok comparator the v in ok comparator monitors the dc output of the pfc and inhibits the pwm if this voltage on v fb is less than its nominal 2.45v. once this voltage reaches 2.45v, which corresponds to the pfc output capacitor being charged to its rated boost voltage, the soft-start begins. pwm control (ramp 2) when the pwm section is used in current mode, ramp 2 is generally used as the sampling point for a voltage representing the current in the primary of the pwms output transformer, derived either by a current sensing resistor or a current transformer. in voltage mode, it is the input for a ramp voltage generated by a second set of timing compo- nents (r ramp2 , c ramp2 ), that will have a minimum value of zero volts and should have a peak value of approximately 5v. in voltage mode operation, feedforward from the pfc output buss is an excellent way to derive the timing ramp for the pwm stage. soft start start-up of the pwm is controlled by the selection of the external capacitor at ss. a current source of 25a supplies the charging current for the capacitor, and start-up of the pwm begins at 1.25v. start-up delay can be programmed by the following equation: f osc 1 t ramp t deadtime + ---------------------------------------------------- = (2) t ramp c t r t in v ref 1.25 C v ref 3.75 C ------------------------------ = (3) t ramp c t r t 0.51 = t deadtime 2.5v 5.5ma ---------------- - c t 450 c t == (4) f osc 1 t ramp ---------------- = (5) f osc 100khz 1 t ramp ---------------- == c ss t delay 25 a 1.25v -------------- - = (6) product specification ml4800 rev. 1.0.5 9/25/01 11 where c ss is the required soft start capacitance, and t delay is the desired start-up delay. it is important that the time constant of the pwm soft-start allow the pfc time to generate suf?cient output power for the pwm section. the pwm start-up delay should be at least 5ms. solving for the minimum value of c ss : caution should be exercised when using this minimum soft start capacitance value because premature charging of the ss capacitor and activation of the pwm section can result if v fb is in the hysteresis band of the v in ok comparator at start-up. the magnitude of v fb at start-up is related both to line voltage and nominal pfc output voltage. typically, a 1.0f soft start capacitor will allow time for v fb and pfc out to reach their nominal values prior to activation of the pwm section at line voltages between 90vrms and 265vrms. generating v cc the ml4800 is a voltage-fed part. it requires an external 15v, 10% (or better) shunt voltage regulator, or some other v cc regulator, to regulate the voltage supplied to the part at 15v nominal. this allows low power dissipation while at the same time delivering 13v nominal gate drive at the pwm out and pfc out outputs. if using a zener diode for this function, it is important to limit the current through the zener to avoid overheating or destroying it. this can be easily done with a single resistor in series with the vcc pin, returned to a bias supply of typically 18v to 20v. the resistors value must be chosen to meet the operating current requirement of the ml4800 itself (8.5ma, max.) plus the current required by the two gate driver outputs. example: with a v bias of 20v, a v cc of 15v and the ml4800 driving a total gate charge of 90nc at 100khz (e.g., 1 irf840 mosfet and 2 irf820 mosfets), the gate driver current required is: choose r bias = 240 ? . the ml4800 should be locally bypassed with a 1.0f ceramic capacitor. in most applications, an electrolytic capacitor of between 47f and 220f is also required across the part, both for ?ltering and as part of the start-up bootstrap circuitry. css 5ms 25 a 1.25v -------------- - 100nf == (6a) i gatedrive 100khz 90nc 9ma == (7) r bias v bias v cc C i cc i g i z ++ --------------------------------- = (8) r bias 20v 15v C 6ma 9ma 5ma ++ -------------------------------------------------- 2 5 0 ? == figure 4. typical trailing edge control scheme ramp veao time vsw1 time ref ea + + osc dff r d q q clk u1 ramp clk u4 u3 c1 rl i4 sw2 sw1 + dc i1 i2 i3 vin l1 u2 ml4800 product specification 12 rev. 1.0.5 9/25/01 leading/trailing modulation conventional pulse width modulation (pwm) techniques employ trailing edge modulation in which the switch will turn on right after the trailing edge of the system clock. the error ampli?er output voltage is then compared with the modulating ramp. when the modulating ramp reaches the level of the error ampli?er output voltage, the switch will be turned off. when the switch is on, the inductor current will ramp up. the effective duty cycle of the trailing edge modu- lation is determined during the on time of the switch. figure 4 shows a typical trailing edge control scheme. in the case of leading edge modulation, the switch is turned off right at the leading edge of the system clock. when the modulating ramp reaches the level of the error ampli?er out- put voltage, the switch will be turned on. the effective duty-cycle of the leading edge modulation is determined dur- ing the off time of the switch. figure 5 shows a leading edge control scheme. one of the advantages of this control technique is that it requires only one system clock. switch 1 (sw1) turns off and switch 2 (sw2) turns on at the same instant to minimize the momentary no-load period, thus lowering ripple volt- age generated by the switching action. with such synchro- nized switching, the ripple voltage of the ?rst stage is reduced. calculation and evaluation have shown that the 120hz component of the pfcs output ripple voltage can be reduced by as much as 30% using this method. typical applications figure 6 is the application circuit for a complete 100w power factor corrected power supply, designed using the methods and general topology detailed in application note 33. figure 5. typical leading edge control scheme ref ea + + osc dff r d q q clk u1 ramp clk u4 u3 c1 rl i4 sw2 sw1 + dc i1 i2 i3 vin l1 veao cmp u2 ramp veao time vsw1 time product specification ml4800 rev. 1.0.5 9/25/01 13 figure 6. 100w power factor corrected power supply, designed using micro linear application note 33 ml4800 ieao i ac i sense v rms ss v dc ramp1 ramp 2 vdc v fb v ref v cc pfc out pwm out gnd dc i lmit r12 68.1k c6 1.5nf c7 150pf c3 0.22 f c26 47 f c2 0.47 f i sense c11 220pf c18 470pf u1 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 r16 10k ? r37 1k ? pri gnd note: d7, d8, d10; 1n966b d3, d5, d6, d12; uf4005 d4; 1n4733a d2; 1n4744a d11; mbr2545ct l1; premier magnetics tsd-1047 l2; premier magnetics vtp-05007 l3; premier magnetics tsd-904 t1; premier magnetics pmgd-03 t2; premier magnetics tsd-735 unused designators; c14, c16, c17, c27, c29, c33, d3, d9, r42, r43, r36, r35 vdc u2 r38 42.2k ? r28 240 ? ref vfb c22 10 f c10 10 f j8 c23 10nf c19 1.0 f d15 1n914 d13 1n914 d14 1n914 rt/ct d8 v buss d12 q2g t2c q3g v cc c31 330pf pwm ilimit d4 5.1v d10 u3 tl431a d11b d11a c28 220pf r10 249k ? r9 249k ? r20 22 ? q1g q1 d1 8a fes16jt d2 15v r1 357k ? r2 357k ? r3 100k ? r4 13.2k ? ac input 85 to 260v c1 0.47 f f1 3.15a br1 4a, 600v kbl06 r5 1.2 ? r8 1.2 ? r7 1.2 ? r25 10k ? r40 470 ? r32 8.66k ? 12v return 12v ret r33 2.26k ? r29 1.2k ? r30 1.5k ? c30 1000 f c32 0.47 f c21 1500 f r34 240 ? c12 10 f 35v c5 100 f c4 4.7nf c25 0.1 f d7 16v d5 600v r39 33 ? r13 383k ? r19 33 ? r14 383k ? d6 600v q2 q3 q4 r18 33 ? r21 2.2 ? r17 3 ? r22 2.2 ? 12v, 100w 12v c24 0.47 f r6 1.2 ? r24 10k ? c20 0.47 f r23 220 ? t1a r15 4.99k ? r26 10k ? r11 412k ? r31 10k ? r44 10k ? l1 irf840a irf840a 1n4744a l2 l3 r27 82k ? t1b c13 0.22 f c15 1.0 f c8 150 f c9 15nf irf820a mbr2545ct 2n3904 1n4733a moc8112 irf820a ml4800 product specification 9/25/01 0.0m 001 stock#ds30004800 ? 2001 fairchild semiconductor corporation disclaimer fairchild semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function or design. fairchild does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. life support policy fairchild s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury of the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com ordering information part number temperature range package ml4800cp 0 c to 70 c 16-pin pdip (p16) ml4800cs 0 c to 70 c 16-pin narrow soic (s16n) ml4800ip -40 c to 85 c 16-pin pdip (p16) ml4800is -40 c to 85 c 16-pin narrow soic (s16n) |
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